module ysyx_22040213_instfetch_syn (
  	  input [63:0] pc,
	  
	  input rst,
	  input clk,
	  
	  // ram enable
	  input instram_req,
//	  input [3:0] wstrb,
	  output addr_ok,
	  output data_ok,
	  output reg [63:0] instt
);
/*verilator lint_off UNUSED*/
	//SRAM PORT//
	
	wire wr  = 1'b0; //inst ram can only be read
	wire [3:0] wen = 4'b1111; //inst ram read four byte a time

	always @(posedge clk)begin
		if(rst)begin
		  instt <= 0;
		end
		if(instram_req && data_ok)begin
		  instt <= o_ram_inst;
	  	end
	end

	// simulated a ram//
	import "DPI-C" function void mpmem_read(input longint raddr, output longint rdata);

	reg [63:0] o_ram_inst;
	assign addr_ok = 1'b1;
	assign data_ok = 1'b1;

	always @(*) begin
		if(rst)begin
		  o_ram_inst =  0;
		end
		else begin
      	  	  mpmem_read(pc, o_ram_inst);
	  end
  	end
 endmodule
